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STHDLS101
AC coupled HDMI level shifter
Features
Converts low-swing alternating current (AC) coupled differential input to high-definition multimedia interface (HDMI) rev 1.3 compliant HDMI level shifting operation up to 2.7 Gbps per lane Integrated 50 termination resistors for AC-coupled differential inputs Input/output transition minimized differential signaling (TMDS) enable/disable Output slew rate control on TMDS outputs to minimize electromagnetic interference (EMI) Fail-safe outputs for backdrive protection No re-timing or configuration required Inter-pair output skew < 250 ps Intra-pair output skew < 10 ps Single power supply of 3.3 V ESD protection: 6 KV HBM on all I/O pins Integrated display data channel (DDC) level shifters. Pass-gate voltage limiters allow 3.3 V termination on graphics and memory controller hub (GMCH) pins and 5 V DDC termination on HDMI connector pins Hot-plug detect (HPD) signal level shifter from HDMI/DVI connector Integrated pull-down resistor on HPD_SINK and OE_N inputs
QFN-48 (7 x 7 mm)

Description
The STHDLS101 is a high-speed high-definition multimedia interface (HDMI) level shifter that converts low-swing AC coupled differential input to HDMI 1.3 compliant open-drain current steering RX-terminated differential output. Through the existing PCI-E pins in the graphics and memory controller hub (GMCH) of PCs or notebook motherboards, the pixel clock provides the required bandwidth (1.65 Gbps, 2.25 Gbps) for the video supporting 720p, 1080i, 1080p with a total of 36-bit resolution. The HDMI is multiplexed onto the PCIe pins in the motherboard where the AC coupled HDMI at 1.2 V is output by GMCH. The AC coupled HDMI is then level shifter by this device to 3.3 V DC coupled HDMI output. The STHDLS101 supports up to 2.7 Gbps, which is enough for 12 bits of color depth per channel, as indicated in HDMI rev 1.3. The device operates from a single 3.3 V supply and is available in a 48-pin QFN package.

Applications

Notebooks PC motherboards and graphic cards Dongles/cable adapters Device summary
Order code STHDLS101QTR
Table 1.
Package QFN-48
Packing Tape and reel
December 2008
Rev 4
1/25
www.st.com 25
Contents
STHDLS101
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1 5.1.2 Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 5.3 5.4 5.5 5.6 5.7
TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 6.2 6.3 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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STHDLS101
Block diagram
1
Block diagram
Figure 1. STHDLS101 block diagram
3/25
System interface
STHDLS101
2
System interface
Figure 2. System inferface
Graphics chipset (GMCH) on the motherboard
PCI-Express SDVO HDMI
Level shifter STHDLS101
HDMI output connector
CS00374
Figure 3.
Cable adapter
4/25
STHDLS101 Figure 4. DP to HDMI/DVI cable adapter
System interface
HPD HDMI/DVI Transmitter
DP Connector
HPD_SOURCE AC_TMDS DDC STHDLS101 HDMI/DVI Cable Adaptor
HPD_SINK DC TMDS DDC
AC_TMDS DDC
PC chipset
HDMI/DVI Connector
5/25
Pin configuration
STHDLS101
3
Pin configuration
Figure 5. STHDLS101 pin configuration
FUNCTION4
FUNCTION3
HPD_SINK
SDA_SINK
DDC_EN
SCL_SINK
VCC33
VCC33 26
33
31
32
30
29
36
35
34
28
27
25
OE_N
GND
GND
GND
GND IN_D1IN_D1+ VCC33 IN_D2IN_D2+ GND IN_D3IN_D3+ VCC33 IN_D4IN_D4+
24 23 22 21 20
GND OUT_D1OUT_D1+ VCC33 OUT_D2OUT_D2+ GND OUT_D3OUT_D3+ VCC33 OUT_D4OUT_D4+
37 38 39 40 41 42 43 44 45 46 47 QFN-48
19 18 17 16 15 14 13
10
11 VCC33
48
GND
FUNCTION1
VCC33
REXT
GND
HPD_SOURCE
SDA_SOURCE
FUNCTION2
SCL_SOURCE
ANALOG2
GND
12
1
2
4
3
5
6
7
8
9
CS000118
6/25
STHDLS101
Pin configuration
3.1
Pin description
Table 2.
Pin number 1 2
Pin description
Name GND VCC33 Type Power Power Ground 3.3 V10% DC supply Function
3
FUNCTION1
Function pins are to enable vendor-specific features or test modes. Vendor-specific For normal operation, these pins are tied to GND or control or test VCC33. pins For consistent interoperability, GND is the preferred default connection for these signals. Function pins are to enable vendor-specific features or test modes. Vendor-specific For normal operation, these pins are tied to GND or control or test VCC33. pins For consistent interoperability, GND is the preferred default connection for these signals. Power Ground Connection to external resistor. Resistor value specified by device manufacturer. Acceptable connections to this pin are: - Resistor to GND - Resistor to 3.3 V - NC (direct connections to VCC or GND are through a 0 resistor for layout compatibility 0 to 3.3 V (nominal) output signal. This is level-shifted version of the HPD_SINK signal. 3.3 V DDC data I/O. Pulled-up by external termination to 3.3 V. Connected to SDA_SINK through voltagelimiting integrated NMOS pass-gate. 3.3 V DDC clock I/O. Pulled-up by external termination to 3.3 V. Connected to SCL_SINK through voltagelimiting integrated NMOS pass-gate. Analog connection determined by vendor. Acceptable connections to this pin are: - Resistor or capacitor to GND - Resistor or capacitor to 3.3 V - Short to 3.3 V or to GND - NC 3.3 V 10% DC supply Ground HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output signal with OUT_D4-.
4
FUNCTION2
5
GND
6
REXT
Analog
7
HPD_SOURCE
Output
8
SDA_SOURCE
I/O
9
SCL_SOURCE
Input
10
ANALOG2
Analog
11 12 13
VCC33 GND OUT_D4+
Power Power Output
7/25
Pin configuration Table 2.
Pin number 14 15 16
STHDLS101 Pin description (continued)
Name Type Function HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential output signal with OUT_D4+. 3.3 V10% DC supply HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output signal with OUT_D3-. HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential output signal with OUT_D3+. Ground HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output signal with OUT_D2-. HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential output signal with OUT_D2+. 3.3 V10% DC supply HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output signal with OUT_D1-. HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential output signal with OUT_D1+. Ground Enable for level shifter path. 3.3 V tolerant low-voltage single-ended input. Internal pull-down enables the device when unconnected.
OUT_D4VCC33 OUT_D3+
Output Power Output
17 18 19
OUT_D3GND OUT_D2+
Output Power Output
20 21 22 23 24
OUT_D2VCC33 OUT_D1+ OUT_D1GND
Output Power Output Output Power
25
OE_N
Input 1 0
OE_N
IN_D termination High-Z 50
OUT_D Outputs High-Z Active
26 27 28
VCC33 GND SCL_SINK
Power Power Output
3.3 V10% DC supply Ground 5 V DDC clock I/O. Pulled-up by external termination to 5 V. Connected to SCL_SOURCE through voltagelimiting integrated NMOS pass-gate. 5V DDC data I/O. Pulled-up by external termination to 5V. Connected to SDA_SOURCE through voltagelimiting integrated NMOS pass-gate.
29
SDA_SINK
I/O
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STHDLS101 Table 2.
Pin number
Pin configuration Pin description (continued)
Name Type Function Low-frequency, 0 to 5 V (nominal) input signal. This signal comes from the HDMI connector. Voltage high indicates "plugged" state; voltage low indicates "unplugged" state. HPD_SINK is pulled down by an integrated 160 K pull-down resistor. Ground Enables bias voltage to the DDC pass-gate level shifter gates. (May be implemented as a bias voltage connection to the DDC pass-gate themselves). 32 DDC_EN Input 0V 3.3 V 33 VCC33 Power DDC_EN Disabled Enabled Pass-gate
30
HPD_SINK
Input
31
GND
Power
3.3 V 10% DC supply
34
FUNCTION3
Function pins are to enable vendor-specific features or test modes. Vendor-specific For normal operation, these pins are tied to GND or control or test VCC33. pins For consistent interoperability, GND is the preferred default connection for these signals. Function pins are to enable vendor-specific features or test modes. Vendor-specific For normal operation, these pins are tied to GND or control or test VCC33. pins For consistent interoperability, GND is the preferred default connection for these signals. Power Power Input Input Power Input Input Power Input Input Ground Ground Low-swing differential input from GMCH PCIE outputs. IN_D1- makes a differential pair with IN_D1+. Low-swing differential input from GMCH PCIE outputs. IN_D1+ makes a differential pair with IN_D1-. 3.3 V10% DC supply Low-swing differential input from GMCH PCIE outputs. IN_D2- makes a differential pair with IN_D2+. Low-swing differential input from GMCH PCIE outputs. IN_D2+ makes a differential pair with IN_D2-. Ground Low-swing differential input from GMCH PCIE outputs. IN_D3- makes a differential pair with IN_D3+. Low-swing differential input from GMCH PCIE outputs. IN_D3+ makes a differential pair with IN_D3-.
35
FUNCTION4
36 37 38 39 40 41 42 43 44 45
GND GND IN_D1IN_D1+ VCC33 IN_D2IN_D2+ GND IN_D3IN_D3+
9/25
Pin configuration Table 2.
Pin number 46 47 48
STHDLS101 Pin description (continued)
Name VCC33 IN_D4IN_D4+ Type Power Input Input 3.3 V10% DC supply Low-swing differential input from GMCH PCIE outputs. IN_D4- makes a differential pair with IN_D4+. Low-swing differential input from GMCH PCIE outputs. IN_D4+ makes a differential pair with IN_D4-. Function
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STHDLS101
Functional description
4
Functional description
This section describes the basic functionality of the STHDLS101 device.
Power supply
The STHDLS101 is powered by a single DC power supply of 3.3 V 10%.
Clocking
This device does not retime any data. The device contains no state machines. No inputs or outputs of the device are latched or clocked.
Reset
This device acts as a level shifter, reset is not required.
OE_N function
When OE_N is asserted (low level), the IN_D and OUT_D signals are fully functional. Input termination resistors are enabled and any internal bias circuits are turned on. The OE_N pin has an internal pull-down that enables the chip if left unconnected. When OE_N is de-asserted (high level), the OUT_D outputs are in high impedance state. The IN_D input buffers are disabled and the IN_D termination resistors are disabled. Internal bias circuits for the differential inputs and outputs are turned off. Power consumption of the chip is minimized. The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and SDA pass-gates are not affected by OE_N. Table 3.
OE_N
OE_N description
Device state Comments Normal functioning state for IN_D to OUT_D level shifting function. Intended for lowest power condition when: * No display is plugged in or * The level shifted data path is disabled HPD_SINK input and HPD_SOURCE output are not affected by OE_N. SCL_SOURCE, SCL_SINK, SDA_SOURCE and SDA_SINK signals and functions are not affected by OE_N.
Asserted Differential input buffers and output (low level) buffers enabled. Input impedance = or unconnected 50 Low-power state. Differential input buffers and terminations are disabled. Differential input buffers are in high-impedance state. OUT_D level shifting outputs are disabled. OUT_D level shifting outputs are in a high-impedance state. Internal bias currents are turned off.
De-asserted (high level)
11/25
Functional description Table 4. OE_N function
OE_N IN_Dx OUT_Dx (TMDS outputs)
STHDLS101
Notes Device disabled. Low power state. Internal bias currents are disabled. Level shifting mode enabled.
De-asserted (high level) Asserted (low level) or unconnected
High-Z
High-Z
50 termination
Enabled
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STHDLS101
Maximum ratings
5
Maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
Symbol VCC VI
Absolute maximum ratings
Parameter Supply voltage to ground potential DC input voltage (TMDS and PCIe ports) Control pins SDA_SINK, SCL_SINK, HPD_SINK pins Value -0.5 to +4.0 -0.5 to +4.0 -0.5 to +4.0 -0.5 to +6 120 1 -65 to +150 300 Human body model 6 Unit V V V V mA W C C kV
IO PD TSTG TL VESD
DC output current Power dissipation Storage temperature Lead temperature (10 sec) Electrostatic discharge voltage on IOs(1)
1. In accordance with the MIL standard 883 method 3015
Table 6.
Symbol JA
Thermal data
Parameter Junction-ambient thermal coefficient QFN-48 48 Unit C/W
13/25
Maximum ratings
STHDLS101
5.1
5.1.1
Table 7.
Symbol VCC33 ICC T
Recommended operating conditions
Power supply and temperature range
Power supply and temperature range
Parameter 3.3 V power supply Maximum power supply current Operating temperature range Total current from VCC 3.3 V power supply -40 Comments Min 3.0 Typ 3.3 Max 3.6 100 85 Unit V mA
o
C
5.1.2
Table 8.
Symbol
Differential inputs (IN_D signals)
Differential input characteristics for IN_D signals
Parameter Comments Tbit is determined by the display mode. Nominal bit rate ranges from 250 Mbps to 2.5 Gbps per lane. Nominal Tbit at 2.5 Gbps = 400 ps. 360 ps = 400 ps - 10% VRX-DIFFp-p=2*|VRX-D+ VRX-D-|. Applies to IN_D signals. The level shifter may add a maximum of 0.02UI jitter VCM-AC-pp=|VRX-D+ + VRX-D-|/2 - VRX-CM-DC. VRX-CM-DC=DC(avg) of |VRX-D+ + VRX-D-|/2 VCM-AC-pp includes all frequencies above 30 kHz. Applies to IN_D+ as well as IN_D- pins (50 20% tolerance) Intended to limit power-up stress on chipset's PCIE output buffers Differential inputs must be in a high impedance state 40 50 Min Typ Max Unit
Tbit
Unit interval
360
ps
VRX-DIFFp-p
Differential input peak to peak voltage Minimum eye width at IN_D input pair
0.175
1.2
V
TRX-EYE
0.8
Tbit
VCM-AC-pp
AC peak common mode input voltage
100
mV
ZRX-DC
DC single-ended input impedance
60
VRX-Bias
RX input termination voltage Single-ended input resistance for IN_Dx when inputs are in high-Z state
0
2
V
ZRX-HIGH-Z
100
K
14/25
STHDLS101
Maximum ratings
5.2
TMDS outputs (OUT_D signals)
The level shifter's TMDS outputs are required to meet the HDMI 1.3 specifications. The HDMI 1.3 specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3 specification.
Table 9.
Symbol
Differential output characteristics for TMDS OUT_D signals
Parameter Single-ended high level output voltage Comments AVCC is the DC termination voltage in the HDMI or DVI sink. AVCC is nominally 3.3 V Min Typ Max Unit
VH
AVCC-10 mV
AVCC
AVCC+10 mV
V
VL
Single-ended low The open-drain output level output pulls down form AVCC voltage Swing down from TMDS termination voltage (3.3 V10%) Measured with TMDS outputs pulled up to AVCC max (3.6 V) through 50 resistors Maximum rise/fall time @ 2.7 Gbps = 148 ps. 125 ps = 148 - 15% Maximum rise/fall time @ 2.7 Gbps = 148 ps. 125 ps = 148 - 15% This differential skew budget is in addition to the skew presented between D+ and D- paired input pins.
AVCC-600 mV
AVCC-500 mV AVCC-400 mV
V
Single-ended VSWING output swing voltage Single-ended current in high-Z state
400 mV
500 mV
600 mV
V
IOFF
10
A
TR
Rise time
125 ps
0.4 Tbit
ps
TF
Fall time
125 ps
0.4 Tbit
ps
TSKEWINTRA
Intra-pair differential skew
10
ps
TSKEWINTER
This lane-to-lane skew Inter-pair lane to budget is in addition to the lane output skew skew between differential input pairs. Jitter budget for TMDS signals as they pass through the level shifter. 7.4 ps = 0.02 Tbit at 2.7 Gbps
250
ps
TJIT
Jitter added to TMDS signals
7.4
ps
15/25
Maximum ratings
STHDLS101
5.3
Table 10.
Symbol
HPD input and output characteristics
HPD_SINK input and HPS_SOURCE output
Parameter HPD_SINK input high level HPD_SINK input low level HPD_SINK input leakage current HPD_SOURCE output high level HPD_SOURCE output low level Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time CL = 10 pF Time required to transition from VOH-HPD_SOURCE to VOLHPD_SOURCE or from VOLHPD_SOURCE to VOHHPD_SOURCE
Comment Low speed input changes state on cable plug/unplug
Min 2 0
Typ 5.0
Max 5.3 0.8 50
Unit V V A
VIH-HPD_SINK VIL-HPD_SINK IIN-HPD_SINK VOHHPD_SOURCE
Measured with HPD_SINK at VIH-HPD max and VILHPD min VCC = 3.3 V10% 2.5 0
VCC 0.02
V V
VOLHPD_SOURCE
THPD
HPD_SINK to HPD_SOURCE propagation delay
200
ns
TRF-HPD
HPD_SOURCE rise/fall time
1
20
ns
CL=10 pF
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STHDLS101
Maximum ratings
5.4
Table 11.
Symb ol VI
DDC input and output chatacteristics
SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics
Parameter Input voltage on SDA_SINK, SCL_SINK pins Comment Voltage on the DDC pins on connector end Min 0 Typ Max 5.5 Unit V
ILKG
VCC = 3.3 V VI = 0.1 VDD to 0.9 VDD to isolated DDC inputs Input leakage current on SDA_SINK, SCL_SINK VDD = external pull-up pins resistor voltage on SDA_SINK and SCL_SINK inputs (maximum of 5.5 V) VCC = 0.0 V VI = 0.1 VDD to 0.9 VDD to DDC sink inputs VDD = external pull-up resistor voltage on SDA_SINK and SCL_SINK inputs (maximum of 5.5 V) SDA_SOURCE, SCL_SOURCE = 0.0 V VI(pp) = 1 V, 100 KHz VCC = 3.3 V, T = 25 C VI(pp) = 1 V, 100 KHz VCC = 3.3 V, T = 25 C IO=3 mA, VO = 0.4 V VCC = 3.3 V
-10
10
A
IOFF
Power-down leakage current on SDA_SINK, SCL_SINK pins
-10
10
A
CI/O CI/O RON
Input/output capacitance (switch off) Input/output capacitance (switch on) Switch resistance
5 10 27 40
pF pF
TPD
Time from DDC_SINK changing state to DDC_SOURCE changing state while the pass gate is DDC_SINK to DDC_SOURCE propagation delay enabled. CL=10 pF RPU=1.5 K (min), 2.0 K (max) Switch time from DDC_EN to the valid state on DDC_SOURCE CL = 10 pF RPU = 1.5 K (min), 2.0 K (max)
8
15
ns
TSX
8
15
ns
17/25
Maximum ratings
STHDLS101
5.5
Table 12.
Symbol
OE_ input characteristics
OE_N input characteristics
Parameter Comment Min 2 0 Measured with OE_N at VIH-OE_N max and VIL-OE_N mix Typ Max VCC33 0.8 200 Unit V V A
VIH-OE_N Input high level VIL-OE_N IIN-OE_N Input low level Input leakage current
5.6
Table 13.
Symbol RHPD
HPD input resistor
HDP input resistor
Parameter HPD_SINK input pull-down resistor Comment Guarantees HPD_SINK is LOW when no display is plugged in Min 130 K Typ 160 K Max 190 K Unit
5.7
Table 14.
Symbol ESD
ESD performance
ESD performance
Parameter MIL STD 883 method 3015 (all pins) Test condition Human body model (HBM) Min -6 Typ Max +6 Unit kV
18/25
STHDLS101
Application information
6
6.1
Application information
Power supply sequencing
A proper power supply sequencing is advised for all CMOS devices. It is recommended to always apply VCC before applying any signals to the input/output or control pins.
6.2
Supply bypassing
Bypass each of the VCC pins with 0.1F and 1nF capacitors in parallel as close to the device as possible, with the smaller valued capacitor as close to the VCC pin of the device as possible.
6.3
Differential traces
The high-speed inputs and TMDS outputs are the most critical parts for the device. There are several considerations to minimize discontinuities on these transmission lines between the connectors and the device. a) b) c) d) Maintain 100 differential transmission line impedance into and out of the device. Keep an uninterrupted ground plane below the high-speed I/Os. Keep the ground-path vias to the device as close as possible to allow the shortest return current path. Layout of the TMDS differential outputs should be with the shortest stubs from the connectors.
Output trace characteristics affect the performance of the STHDLS101. Use controlled impedance traces to match trace impedance to both the transmission medium impedance and termination resistor. Run the differential traces close together to minimize the effects of the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities in the differential trace layout. Avoid 90 C turns and minimize the number of vias to further prevent impedance discontinuities.
19/25
Package mechanical data
STHDLS101
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
20/25
STHDLS101 Figure 6. QFN-48 (7 x 7 mm) package outline
Package mechanical data
21/25
Package mechanical data Table 15.
Symbol Min A A1 A2 A3 b D D2 E E2 e L ddd 0.18 6.85 2.25 6.85 2.25 0.45 0.30 0.80 Typ 0.90 0.02 0.65 0.25 0.23 7.00 4.70 7.00 4.70 0.50 0.40 0.30 7.15 5.25 7.15 5.25 0.55 0.50 0.08 0.18 6.90 Max 1.00 0.05 1.00 Min 0.80 Typ 0.85 0.01 0.65 0.20 0.23 7.00
STHDLS101
QFN-48 (7 x 7 mm) package mechanical data
Millimeters Inches Max 1.00 0.05
0.30 7.10
See exposed pad variations 6.90 7.00 7.10
See exposed pad variations 0.45 0.30 0.50 0.40 0.55 0.50 0.08
Figure 7.
QFN-48 tape information
22/25
STHDLS101 Figure 8. Reel information
Package mechanical data
0084694_J
Table 16.
A
Reel mechanical data (dimensions in mm)
C 13 0.25 N 100 T 16.4
330.2
23/25
Revision history
STHDLS101
8
Revision history
Table 17.
Date 15-Apr-2008 23-Apr-2008 10-Jun-2008
Document revision history
Revision 1 2 3 Initial release. Modified: Figure 5. Document status promoted from preliminary data to datasheet. Updated: Features section, Table 2: Pin description on page 7 and Chapter 4 and Chapter 5: Maximum ratings on page 13. Added: Figure 3: Cable adapter on page 4, Figure 4: DP to HDMI/DVI cable adapter on page 5, Figure 8: Reel information on page 23 and Table 16: Reel mechanical data (dimensions in mm) on page 23. Changes
01-Dec-2008
4
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STHDLS101
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